Power Management

Learn software-controlled power management with multiple-choice questions: dynamic and static power, DVFS and OS frequency control, power gating versus clock gating, sleep states and thermal throttling.

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Power Management: key points

Both smartphone battery life and data-center electricity bills depend heavily on how chips use power. Power in CMOS circuits consists of dynamic power, consumed each time signals switch, and static power, consumed through leakage even when idle, and each calls for different countermeasures.

This topic covers how operating systems and firmware make use of hardware mechanisms such as DVFS, which lowers voltage and frequency to match the load; clock gating, which stops the clock to unused circuits; and power gating, which cuts off their supply entirely. It also covers CPU sleep and performance states and the idea behind thermal throttling when temperatures climb too high.

All Power Management questions (50)

  1. In the CMOS dynamic power formula P = αCV²f, what does α represent?
  2. What is the dynamic power of a circuit with activity factor α = 0.1, switched capacitance C = 1 nF, supply voltage V = 1 V and frequency f = 1 GHz?
  3. With the supply voltage unchanged, only the clock frequency is halved. What happens to the dynamic energy needed to finish a fixed amount of computation?
  4. Assume DVFS can lower the supply voltage in proportion to frequency. When frequency is halved, roughly what happens to dynamic power and to the dynamic energy for a fixed amount of computation?
  5. Which describes static (leakage) power in CMOS circuits?
  6. How does leakage power change as chip temperature rises, and what problem can result?
  7. Which describes power gating?
  8. Which correctly pairs a caveat of power-gated blocks with its countermeasure?
  9. Which correctly compares clock gating and power gating?
  10. In power gating, why are a block's power switches often turned on gradually in sequence rather than all at once?
  11. What is the role of the isolation cells placed between a powered-off block and running blocks?
  12. What is the role of a level shifter inserted when passing signals between two blocks running at different supply voltages?
  13. What is the main purpose of dividing an SoC into multiple power domains?
  14. What is the break-even time used to decide whether powering off an idle block pays off?
  15. Which describes CPU C-states?
  16. Which describes CPU P-states?
  17. When does "race to idle" (finishing work fast and then sleeping deeply) tend to save energy?
  18. What is the role of a governor, such as a cpufreq governor, that sets CPU frequency in Linux and other OSes?
  19. Which describes CPU turbo operation (such as Turbo Boost)?
  20. Which describes thermal throttling?
  21. Some CPU power limits let the chip run above the long-term average limit (close to TDP) for short periods. Why does this work?
  22. What is the most suitable use of features such as Intel RAPL that let software measure CPU and memory power and set caps?
  23. Which describes ACPI, used in PCs and similar systems?
  24. In smartphone SoCs combining high-performance and efficient cores, why does running light work on the efficient cores use less energy?
  25. Which describes the idea behind adaptive voltage scaling (AVS)?
  26. Which is NOT a reason chips need margin in their supply voltage?
  27. What is an advantage of placing the regulators that generate CPU supply voltages inside the chip or package rather than on the motherboard (integrated regulators)?
  28. Why is the energy-delay product (EDP) sometimes preferred over energy alone in evaluating low-power designs?
  29. What is the closest efficiency of a linear regulator (LDO) producing 1.0 V from a 1.8 V input (ignoring the regulator's own quiescent current)?
  30. A device drawing 300 mA on average runs from a 3000 mAh battery. Roughly how many hours does it run (ignoring voltage drop and similar)?
  31. What is the difference between power and energy?
  32. Which metric is most suitable for comparing processor energy efficiency?
  33. In today's chips, which statement comparing the energy of moving data and computing is generally correct?
  34. Among DRAM power-saving states, which describes self-refresh?
  35. DRAM operated at high temperature may require shorter refresh intervals. Which pairs the reason with the effect on power correctly?
  36. To cut power on a microcontroller, what should be done with unused peripherals such as timers and UARTs?
  37. What is the role of a PMIC (power management IC) used in smartphones and similar devices?
  38. In chips using multiple supply voltages, why must the power-up order (power sequencing) be observed?
  39. What characterizes near-threshold operation, running with supply voltage lowered close to the transistor threshold?
  40. As supply voltage is lowered, total energy per operation reaches a minimum at some voltage and then rises if voltage is lowered further. Why?
  41. A 50 W CPU is fitted with a cooler of thermal resistance 0.5 K/W. Roughly how many degrees above ambient does the chip run (ignoring other heat paths)?
  42. Why are temperature sensors often placed at many locations within a large chip?
  43. In data centers packed with high-performance AI GPUs, why is liquid cooling spreading alongside air cooling?
  44. Which describes PUE, a metric of data center power efficiency?
  45. Why do smartphone SoCs play video using dedicated video decoder circuits rather than the general-purpose CPU?
  46. Why does an OS slightly shift and align the wake-up times of many programs' timers (timer coalescing)?
  47. What is the idea behind the tickless kernel used in Linux and other OSes?
  48. What is the Arm WFI (Wait For Interrupt) instruction used for?
  49. What is commonly used to wake a battery-powered device from sleep at a set time?
  50. If only the supply voltage is lowered by 10% (all else equal), by roughly what percentage does dynamic power fall?

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