What is RTL (register-transfer level)?
A design abstraction that describes circuits by how data moves and is processed between registers. It is written in Verilog or VHDL and serves as the input to logic synthesis.
Field: LSI design flow and EDA
RTL (register-transfer level) in the explanations
In RTL design, registers and the data flow between them are described in hardware description languages such as Verilog HDL (and its extension SystemVerilog) and VHDL.
Which hardware description languages are mainly used in RTL…High-level synthesis takes behavioral descriptions written in C/C++ and automatically decides allocation of operators and registers and the order of operations (scheduling), generating RTL.
What is the technology called that automatically generates …Coverage indicates which lines and branches of RTL code were executed during verification (code coverage) and how many of the functions and scenarios defined in the specification were checked (functional coverage).
In RTL verification, which metric is used to evaluate how t…
Questions that mention RTL (register-transfer level) (6)
- Which hardware description languages are mainly used in RTL design?
- What is the technology called that automatically generates RTL from algorithm descriptions written in C or C++?
- In RTL verification, which metric is used to evaluate how thoroughly verification has been done?
- Which is the correct order of a typical digital LSI design flow?
- Which correctly describes logic synthesis?
- In low-power design, which standard format describes the "power intent", such as power domains, power shutoff and level shifters, separately from the circuit description?
Related terms
Logic synthesis Netlist High-level synthesis (HLS) Place and route Clock gating DRC (design rule check) FPGA LVS PDK (process design kit) SPICE