Interconnect processes

Learn the basics of interconnect processes — copper wiring and the damascene process, low-k materials and RC delay — through multiple-choice questions.

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Interconnect processes: key points

In an LSI, transistors are connected by many layers of metal wiring. As scaling progressed, delay caused by wire resistance and capacitance (RC delay) came to limit performance, and wiring materials have been improved accordingly.

Copper wiring, which has lower resistance than aluminum, is hard to dry-etch, so it is made by the damascene process: filling trenches and removing the excess by CMP. Low-k materials with low dielectric constants are used for the interlayer insulators.

All Interconnect processes questions (50)

  1. What is the main reason the wiring material of advanced LSIs was changed from aluminum (Al) to copper (Cu)?
  2. Which correctly describes the damascene process commonly used to form copper wiring?
  3. What is the main purpose of using low-k (low dielectric constant) materials for interlayer dielectrics?
  4. What is the main purpose of barrier metals such as Ta and TaN in copper wiring?
  5. Which correctly describes a via in multilevel interconnects?
  6. If a wire's length is doubled without changing its cross-section or spacing, approximately how many times larger does its RC delay become?
  7. What is the purpose of forming silicides such as NiSi on the surfaces of a transistor's source, drain and gate?
  8. Which metal has been widely used to fill contact holes connecting transistors to the lowest wiring layer?
  9. When copper wires become very narrow, what is the main reason their effective resistivity rises?
  10. In multilevel interconnects, what is the main reason upper-level wires are made wider and thicker?
  11. What is the main purpose of the technique that makes part of the insulator between wires a cavity (air gap)?
  12. Which correctly describes backside power delivery, which is being introduced in advanced logic?
  13. What is the phenomenon called in which current flowing through the resistance of power wiring lowers the supply voltage that reaches circuits?
  14. What is the phenomenon called in which, through capacitive coupling between adjacent wires, a signal change on one wire appears as noise on the other?
  15. What is the main purpose of placing a cap layer such as cobalt on top of copper wiring?
  16. In Black's equation for wire lifetime under electromigration, which factors shorten the lifetime?
  17. Which is closest to the number of wiring layers in advanced logic LSIs?
  18. What is an advantage of metals such as ruthenium (Ru), being considered as alternatives to copper for fine wiring?
  19. What is the film called that is formed on the top of a chip to protect the internal circuits from moisture, contamination and mechanical damage?
  20. Which metal has been used in many LSIs for the top-level bond pads where wire bonding is done?
  21. What is the method called that fills wiring trenches and vias with copper at the same time and finishes them with a single CMP step?
  22. What is the role of the thin copper film sputtered before filling copper by electroplating?
  23. What problems occur when copper filling is incomplete and a void remains in a via?
  24. If the spacing between adjacent wires in the same layer is halved, approximately how does the capacitance between them change? (Approximate as parallel plates.)
  25. Which technique forms vias self-aligned to wiring trenches to tolerate misalignment between upper and lower wiring layers?
  26. For wiring with a resistivity of 2 µΩ·cm, 1 mm long, with width and thickness of 100 nm each, approximately what is the resistance?
  27. Where are voids due to electromigration likely to form?
  28. In highly scaled LSIs, how has wiring delay trended compared with gate delay?
  29. What problem must be watched for when etching or ashing low-k films?
  30. What is the time-dependent dielectric breakdown of the insulator between wires called, which is becoming more important as wire spacing shrinks?
  31. What is the main role of the wiring inside an LSI?
  32. Which correctly describes "multilevel wiring" in an LSI?
  33. Which is closest to the resistivity of copper (Cu) at room temperature? (Bulk value)
  34. Which set correctly lists the main properties required of LSI wiring materials?
  35. What is the basic role of the interlayer dielectric that fills the space between wires?
  36. Why has an Al-Cu alloy with about 0.5% copper been used for aluminum wiring?
  37. What is the phenomenon called in which electroplated Cu films, simply left at room temperature, grow larger grains over time and drop in resistivity?
  38. What is the main purpose of the design practice of placing two or more vias, rather than one, wherever possible to connect upper and lower wires?
  39. Which term refers to the contacts and local interconnects that connect the transistors to the multilevel wiring?
  40. In scaled multilevel wiring, what is the main reason via resistance has become a problem?
  41. Which statement about the capacitance of a wire is correct?
  42. What is the effect of increasing a wire's thickness (height) without changing its width?
  43. In chips using mechanically weak low-k films, what is the problem called in which stress during packaging cracks or delaminates the films?
  44. What film is commonly placed on top of Cu wiring to act both as a diffusion barrier toward the dielectric and as an etch stop?
  45. In electromigration testing, wires shorter than a certain length show greatly extended lifetimes, with almost no degradation. What is this phenomenon called?
  46. When a wire becomes narrower than its grains so that grain boundaries line up across the wire, what is this structure called, and how does it affect electromigration?
  47. When high-frequency signals flow in a wire, what is the phenomenon called in which current concentrates near the conductor surface and the effective resistance rises?
  48. What is the design practice called in which active devices and wiring are placed directly beneath the bond pads used for wire bonding and the like?
  49. Which technique deposits a Cu alloy with a small addition of manganese or similar and, through annealing, lets a thin barrier form spontaneously at the interface with the dielectric?
  50. For long, wide wires such as the clock network of a chip running at several GHz, which wire property must be considered in addition to resistance and capacitance?

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