I/O Interfaces & Buses

Learn about I/O interfaces and buses with multiple-choice questions: PCI Express lanes and bandwidth calculations, SerDes serial links, USB, on-chip buses such as AXI, CXL, and bandwidth versus latency.

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I/O Interfaces & Buses: key points

Inside a computer, components such as the CPU, memory, GPU, storage and network are connected by various interfaces. For high-speed links, serial transmission, which sends very fast signals over a few wires, has replaced parallel buses with many wires, enabled by transceiver circuits called SerDes.

This topic covers calculating bandwidth from PCI Express lane count and per-lane speed, encoding efficiency, USB basics, on-chip buses such as AXI that connect blocks within a chip, and CXL for sharing memory. Understanding that bandwidth and latency are different quantities reveals what actually limits performance.

All I/O Interfaces & Buses questions (50)

  1. Why have high-speed connections between chips and boards moved from parallel transmission over many wires to serial transmission over a few fast wires?
  2. What is the role of a SerDes (serializer/deserializer) in high-speed serial links?
  3. Why do high-speed serial links use differential signaling, sending opposite signals on two wires?
  4. What is the role of the clock and data recovery (CDR) circuit in a high-speed serial receiver?
  5. What has been the purpose of 8b/10b encoding (sending 8 data bits as a 10-bit code) in serial links?
  6. On a link using 8b/10b encoding with a signaling rate of 5 Gb/s, what is the effective data rate?
  7. Which is closest to the efficiency of the 128b/130b encoding adopted from PCI Express 3.0 onward?
  8. Which describes a "lane" in PCI Express?
  9. What is closest to the effective one-direction bandwidth of a PCI Express 3.0 x16 link (8 GT/s per lane, 128b/130b encoding)?
  10. For PCI Express generations 3 through 6, how does the per-lane signaling rate change with each generation?
  11. What is a characteristic of PAM4 (four-level pulse amplitude modulation), adopted in PCI Express 6.0?
  12. Why does forward error correction (FEC) become more important with PAM4 than with NRZ?
  13. What happens when an x4 PCI Express SSD is plugged into a full-length x16 slot on a motherboard (assuming the slot is wired for at least x4)?
  14. Which statement about the structure of PCI Express is correct?
  15. How does communication in PCI Express work?
  16. What does the PCI Express data link layer do about bit errors during transmission?
  17. How are the registers and memory of a PCI Express device made accessible to the CPU?
  18. What is a characteristic of MSI (message-signaled interrupts) used in PCI Express?
  19. What is the difference between bandwidth and latency in interface performance?
  20. On a link with 10 GB/s bandwidth and 1 µs latency, roughly how long does it take to send 64 bytes once (time = latency + size ÷ bandwidth)?
  21. Which is most effective for speeding up a program that exchanges thousands of small pieces of data with a device one at a time?
  22. Which statement about how USB communication works is correct (for conventional USB, excluding USB4)?
  23. Which statement about USB Type-C is correct?
  24. Which describes USB Power Delivery (USB PD)?
  25. Among USB transfer types, what is characteristic of isochronous transfers?
  26. Which describes hot plugging, supported by USB and some PCI Express setups?
  27. Which bus from Arm's AMBA specifications is widely used to connect blocks such as CPUs, memory controllers and peripherals inside an SoC?
  28. What is a characteristic of the AXI bus?
  29. In the VALID/READY handshake used on each AXI channel, when is data transferred?
  30. What is the advantage of burst transfers in AXI?
  31. In AXI, what is the advantage of issuing the next read request without waiting for the previous one's response (having multiple outstanding requests)?
  32. What is AXI4-Lite mainly used for?
  33. What is a characteristic of AXI4-Stream?
  34. Why have large SoCs adopted a network-on-chip (NoC) instead of a single shared bus?
  35. Which describes CXL (Compute Express Link)?
  36. What is an advantage of memory expansion using CXL (CXL memory)?
  37. Which correctly lists the three protocols that make up CXL?
  38. What is the role of equalizers (such as CTLE and DFE) in high-speed serial receivers?
  39. Which statement about the eye diagram used to assess high-speed serial signal quality is correct?
  40. Why does raising serial link speed make it harder to send signals over board traces of the same length, sometimes requiring retimers along the way?
  41. What does a requirement of "bit error rate (BER) at most 10^-12" for a high-speed serial link mean?
  42. Why are high-speed signal traces designed so that their characteristic impedance matches the transmit and receive circuits?
  43. High-speed links such as 100-gigabit Ethernet are sometimes built by bundling, for example, four 25 Gb/s lanes. Which describes this approach?
  44. What is the purpose of spread-spectrum clocking (SSC), used in PCI Express and elsewhere?
  45. What does it mean that a PCI Express lane is full duplex?
  46. Which describes the credit-based flow control used in PCI Express?
  47. In AI systems with many GPUs, why are dedicated high-speed GPU-to-GPU links (such as NVIDIA NVLink) used in addition to PCI Express?
  48. In PCI Express, sending many packets that each write 64 bytes yields effective bandwidth well below the theoretical figure. What is the main reason?
  49. Which statement is correct about DMA using a ring of descriptors in memory, as widely used by network cards and NVMe SSDs?
  50. Which statement is correct about PCI Express link power saving (the L0s and L1 states of ASPM)?

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