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Hardware Security: Advanced Topics and Trends

Learn with multiple-choice questions, including calculations: VM-based TEEs (AMD SEV-SNP, Intel TDX and Arm CCA) and confidential computing, memory integrity protection and its cost, verifying attestation reports, GPU confidential computing, memory and control-flow protection with CHERI, MTE, pointer authentication and shadow stacks, Rowhammer with TRR, PRAC and the limits of ECC, MDS with retpoline and IBRS, the performance cost of mitigations, post-quantum cryptography in hardware (the number-theoretic transform, key sizes and implementation pitfalls), open roots of trust and DICE, secure firmware update, HBOMs, chiplet security, split manufacturing, IC camouflaging and logic locking, reverse engineering, FIPS 140-3, Common Criteria, PSA Certified and SESIP, authenticated debug and lifecycle states, scan chains, and fault injection by voltage glitches, lasers and electromagnetic pulses.

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Hardware Security: Advanced Topics and Trends: key points

With the spread of cloud computing, AI and IoT devices, both what hardware security protects and how it is attacked have changed greatly. Confidential computing that protects data even from a cloud provider's administrators, hardware that stops pointer errors, cryptographic hardware for the era of quantum computers, and protecting a semiconductor supply chain involving many companies are major themes today. Building on the basics in "Hardware Security", this topic covers newer and deeper material.

It starts with confidential computing: the difference between VM-based and enclave-based TEEs and the trusted computing base (TCB), why integrity protection is needed in addition to encryption and a calculation of its storage cost, what a verifier checks in an attestation report, Arm CCA realms and confidential computing that includes GPUs. It continues with CHERI capabilities, a calculation of the probability that MTE tags match by chance, pointer authentication, and control-flow integrity through shadow stacks and protection of indirect branches. For attacks on DRAM it covers why Rowhammer becomes more likely with scaling, research that bypassed TRR, the limits of ECC, PRAC in DDR5 and a calculation relating refresh rate to activation counts; for transient execution attacks, MDS, retpoline and IBRS, and a calculation of the slowdown caused by mitigations. The second half covers speeding up polynomial multiplication with the number-theoretic transform, ML-KEM key sizes, implementation precautions for decapsulation, hardware designed so that cryptography can be replaced, OpenTitan and Caliptra, DICE, A/B updates with anti-rollback, HBOMs, trust between chiplets, split manufacturing, IC camouflaging and logic locking, and protecting keys against reverse engineering. It ends with FIPS 140-3 levels, Common Criteria EALs, composition in PSA Certified and SESIP, authenticated debug, lifecycle states and RMA, protecting scan chains, and fault injection by voltage glitches, lasers and electromagnetic pulses, including calculations of success probabilities and of the effect of countermeasures. The aim is to understand principles and countermeasures from the viewpoint of designers and defenders, not attack procedures. The values in the calculation questions, including those of the wrong choices, have been checked by computing them in Python. Product names, standard versions and years are given as of the time stated in each question. Side-channel attacks, Spectre, Meltdown and KPTI, power analysis, the basics of fault injection and Rowhammer, secure boot, TPMs, TEEs, TrustZone and enclaves, PUFs, true random number generators, hardware Trojans and disabling JTAG are covered in "Hardware Security"; the ML-KEM and ML-DSA standards and HSMs in "Applied Cryptography"; DRAM refresh and the name of the Rowhammer phenomenon in "DRAM"; chiplets and UCIe in "Advanced packaging (3D and chiplets)"; scan design in "Testing and inspection"; A/B firmware updates in "Embedded Systems & Firmware"; and ISO/SAE 21434 in "Automotive Semiconductors and Functional Safety".

All Hardware Security: Advanced Topics and Trends questions (40)
  1. Among the TEEs used in confidential computing, which correctly describes the difference between VM-based TEEs that protect a whole virtual machine (such as AMD SEV-SNP and Intel TDX) and enclave-based TEEs that protect part of an application (such as Intel SGX)?
  2. Why was encrypting virtual machine memory alone considered insufficient in VM-based TEEs, so that mechanisms protecting memory integrity were added, as in AMD SEV-SNP?
  3. Consider a circuit that adds tamper detection and replay protection to memory encryption. For every 64-byte cache line, an 8-byte MAC (a code for detecting tampering) and an 8-byte counter that increases on every write are stored in main memory. Ignoring the tree that protects the counters, what is the extra storage needed as a proportion of the amount of data protected?
  4. In confidential computing, a user's verification server (the verifier) checks the attestation report received from a VM-based TEE before handing over the key that decrypts the data. Which is the most appropriate set of things for the verifier to check?
  5. As of the mid-2020s, some data-center GPUs provide features that let them be used for confidential computing together with a CPU TEE. Which correctly describes the idea of this mechanism?
  6. Which correctly describes the realm introduced in Arm CCA (Confidential Compute Architecture)?
  7. Which correctly describes the capabilities used in the instruction-set extension called CHERI?
  8. In Arm MTE (Memory Tagging Extension), a 4-bit tag is attached to every 16 bytes of memory and a 4-bit tag is also placed in the upper bits of the pointer, and the CPU checks on every access whether the two match. Consider the error of accessing a freed region through an old pointer to it. If the new tag given when the region is reallocated is chosen uniformly at random from the 16 possibilities, what is the probability that the tags match by chance and the error is missed?
  9. Which correctly describes the mechanism of Arm pointer authentication (PAC)?
  10. Which correctly describes the hardware shadow stack adopted in Intel CET (Control-flow Enforcement Technology) and elsewhere?
  11. Regarding hardware features that support control-flow integrity, which correctly pairs what protects returns from functions with what protects indirect calls and jumps such as those through function pointers?
  12. Which correctly explains why Rowhammer is said to become more likely as DRAM is scaled down?
  13. Which correctly explains why Rowhammer protection by in-DRAM TRR (target row refresh) has been bypassed in research?
  14. What is wrong with the idea that "if ECC memory is used, there is no need to worry about Rowhammer"?
  15. Which correctly describes the idea of PRAC (per-row activation counting), added to the DDR5 standard updated in 2024 (JESD79-5C)?
  16. For simplicity, take the shortest interval at which rows in the same bank can be activated to be tRC = 50 ns. With a refresh period of 64 ms, the maximum number of times a neighbouring row can be activated between one refresh of a given row and the next is 64 ms ÷ 50 ns. What is this maximum number when the refresh rate is doubled?
  17. Which correctly describes the characteristics of the vulnerability called MDS (Microarchitectural Data Sampling), published in 2019?
  18. Which correctly pairs the descriptions of retpoline and IBRS, countermeasures against the Spectre variant that abuses indirect branch prediction (branch target injection)?
  19. A task took 10 seconds before mitigations for speculative execution were applied and made 5 million system calls during that time. Assume that the mitigations increase the processing time per system call from 0.4 µs to 0.6 µs and leave the time of everything else unchanged. By what proportion does the total time of the task increase?
  20. Lattice-based post-quantum cryptography repeatedly multiplies polynomials of degree n = 256. If the naive method of multiplying every pair of coefficients needs about n² multiplications and the method using the number-theoretic transform (NTT) needs about n log₂ n, which is closest to the factor by which the NTT reduces the number of multiplications?
  21. The public key of ML-KEM-768 is 1,184 bytes and its ciphertext 1,088 bytes, while the public value of the elliptic-curve key exchange X25519 is 32 bytes. How many times larger than the X25519 public value is the ML-KEM-768 public key?
  22. In ML-KEM decapsulation, the ciphertext is rebuilt from the result of decrypting the received ciphertext with the private key and compared with the received ciphertext. Which is a correct implementation precaution for this part?
  23. You are designing an SoC for an embedded device that will be used for more than 10 years. Which is an appropriate hardware and firmware design to prepare for future cryptographic migration (such as the move to post-quantum cryptography)?
  24. What is the most appropriate benefit of efforts such as OpenTitan and Caliptra that publish the designs of root-of-trust circuits?
  25. Which correctly describes the mechanism of DICE (Device Identifier Composition Engine) defined by the TCG?
  26. In a device that updates firmware using two areas, side A and side B, when is the most appropriate time to advance the minimum version number recorded in eFuses for anti-rollback to the new version number?
  27. Which correctly describes a hardware bill of materials (HBOM)?
  28. Which is an appropriate way to think about security when combining chiplets from several companies in one package?
  29. Which correctly pairs techniques that protect semiconductor designs with the untrusted party each mainly assumes?
  30. Assuming reverse engineering that reads the circuit by removing a chip's layers one at a time and imaging them with an electron microscope, or by imaging its interior with X-rays, which is an appropriate design approach?
  31. Regarding security levels 1 to 4 of FIPS 140-3, the certification standard for cryptographic modules, which correctly describes the requirements for physical security?
  32. What does the EAL (evaluation assurance level) of Common Criteria (ISO/IEC 15408), the international standard for evaluating security products, represent?
  33. Which correctly describes the idea of composition emphasized in PSA Certified and SESIP, security certification frameworks for IoT devices?
  34. Which is the most appropriate design for authenticated debugging that lets only the manufacturer's engineers open the debug port of shipped products?
  35. The lifecycle state of a security chip is managed in stages such as test, production and failure analysis of returned parts (RMA). Which is an appropriate way to handle moving from the production state to the RMA state for failure analysis?
  36. Which correctly pairs the reason why scan chains for scan testing can become an attack path in a chip that performs cryptographic processing with a countermeasure?
  37. Which correctly explains the main reason a chip malfunctions under a voltage glitch that lowers the supply voltage for an instant?
  38. Among fault injection attacks, which correctly pairs the characteristics of methods using a laser and methods using electromagnetic pulses?
  39. A fault injection attempt succeeds with a probability of 0.1% each time, and the results of attempts are independent. Which is closest to the probability of at least one success in 1,000 attempts?
  40. Suppose a firmware signature check is skipped by a single fault injection attempt with a probability of 1/1,000. The same check is now done in two places, so that the attack succeeds only if both are skipped. If one attempt can target both places at once and each is skipped independently with probability 1/1,000, what is the expected number of attempts until the attack succeeds?

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