ISA & Assembly

Learn the basics of instruction sets and assembly language with multiple-choice questions: instruction formats, addressing modes, core RISC-V instructions, calling conventions and stack frames.

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ISA & Assembly: key points

An instruction set architecture (ISA) is the contract between software and hardware. It defines which instructions exist, how they are encoded as bits, and how registers and memory are specified. Any CPU that honors the same ISA can run the same programs, however different its internals.

Assembly language writes machine instructions in human-readable form. Knowing the core RISC-V instructions, register usage, how arguments and return values are passed between functions (the calling convention) and how stack frames are built shows you what compilers generate and how programs actually run on a CPU.

All ISA & Assembly questions (50)

  1. Which statement is correct about two CPUs that implement the same instruction set architecture (ISA)?
  2. What is a characteristic of a load-store architecture such as RISC-V?
  3. What is the property of register x0 (zero) in RISC-V?
  4. Which describes the general-purpose integer registers of RISC-V RV32I (the 32-bit base integer instruction set)?
  5. What is the relationship between assembly language and machine code?
  6. Which real instruction does the assembler use for the RISC-V pseudo-instruction "nop" (do nothing)?
  7. What is the difference between the RISC-V "add" and "addi" instructions?
  8. After running the RISC-V code above, what is the value in register a2?
  9. What does the RISC-V instruction "lw t0, 8(sp)" do?
  10. In the RISC-V conditional branch "beq a0, a1, label", how is the target address of label encoded?
  11. What is an advantage of using PC-relative addressing for branches and jumps?
  12. Which statement about instruction length in the RISC-V base ISA and in x86 is correct?
  13. What is the main advantage of making instructions a fixed length?
  14. In RISC-V instructions, each register field (rd, rs1, rs2) is 5 bits wide. Why?
  15. The immediate of RISC-V addi is a 12-bit signed integer. What range can it represent?
  16. In RISC-V, what is the usual way to put a 32-bit constant that does not fit in a 12-bit immediate (e.g. 0x12345678) into a register?
  17. To build the constant 0x12345FFF in RISC-V with lui and addi, which pair is correct?
  18. What does the RISC-V auipc instruction (add upper immediate to PC) do?
  19. On RISC-V RV32I, what 32-bit value is in t0 after "addi t0, zero, -1"?
  20. A byte in memory holds 0x80. Which pair correctly gives the 32-bit register value after loading it with RISC-V lb and with lbu?
  21. How do RISC-V and x86 differ in their mechanism for conditional branches?
  22. What does the RISC-V instruction "slt t0, a0, a1" do?
  23. When the RISC-V code above finishes, what is the value in t0?
  24. RISC-V conditional branches (B-type) encode the distance as a 13-bit signed byte offset whose lowest bit is always 0 and not stored. Roughly what range can a branch reach directly?
  25. What does the RISC-V instruction "jal ra, func" do?
  26. Which real instruction executes the RISC-V pseudo-instruction "ret"?
  27. What is the main purpose of defining a calling convention?
  28. In the standard RISC-V calling convention, which registers pass integer arguments and return values?
  29. In the standard RISC-V calling convention, when calling a function with ten integer arguments, where are the ninth and tenth passed?
  30. In the RISC-V calling convention, s0-s11 are callee-saved registers. What does that mean?
  31. In the RISC-V calling convention, t0-t6 are caller-saved. If a function wants to keep using a value in t0 after calling another function, what should it do?
  32. A function that calls no other functions (a leaf function) often does not need to save ra on the stack. Why?
  33. What is the purpose of executing "addi sp, sp, -16" at the start of a RISC-V function?
  34. The standard RISC-V calling convention requires sp to be a multiple of 16 bytes on function entry. What is the main reason?
  35. The code above is the start (prologue) of a function. What does it do?
  36. What is an advantage of using a frame pointer (s0/fp in RISC-V) inside a function?
  37. In RISC-V, what happens if a recursive function (one that calls itself) forgets to save ra on the stack?
  38. On little-endian RISC-V, a register holding 0x12345678 is stored with sw to address 0x100. What value does lbu then read from address 0x101?
  39. In RISC-V, what can happen when the address of a 4-byte lw is not a multiple of 4 (misaligned)?
  40. The RISC-V instruction "slli t0, a0, 3" makes t0 how many times the value of a0 (ignoring overflow)?
  41. a0 holds the start address of an int (4-byte) array a, and a1 holds an index i. What does the code above load into a2?
  42. Which statement is correct about designs like x86, where an arithmetic instruction such as "add eax, [rbx]" can use a memory value directly?
  43. How do today's high-performance x86 CPUs execute complex instructions internally?
  44. What instructions does the RISC-V M extension add to the base integer instruction set?
  45. What is the main purpose of the RISC-V C extension (compressed instructions)?
  46. When C's "a * b" (multiplying two ints) is compiled for an RV32I CPU without the M extension, what generally happens?
  47. What is true of the branch delay slot found in older ISAs such as MIPS (the rule that the one instruction right after a branch always executes, taken or not)?
  48. On 64-bit RV64I, how does lw place the 32-bit value it loads into a 64-bit register?
  49. Which correctly describes an ABI (application binary interface)?
  50. How is a call through a C function pointer, "(*fp)(x)", generally performed in RISC-V?

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