What is Bit line?

Bit line in the explanations

• On readout, the cell's charge is shared with the bit line.

  Why is the voltage change on the bit line very small when D…

• NOR flash is named for its cells being connected in parallel to the bit line, resembling a NOR structure.

  When is the output of a two-input NOR gate 1?

• Connecting the cell capacitor to the bit line shares its charge with the bit line's large parasitic capacitance, destroying the original state (destructive read).

  Which correctly describes the read operation of DRAM?

Questions that mention Bit line (12)

1. Why is the voltage change on the bit line very small when DRAM is read?
2. When writing to an SRAM cell, one bit line is pulled down to 0 V to flip the cell's state. What condition is required of the access transistor?
3. When is the output of a two-input NOR gate 1?
4. Which correctly describes the read operation of DRAM?
5. In DRAM access, what is the operation called that closes the open row and returns the bit lines to an intermediate voltage to prepare for activating the next row?
6. In DRAM cell arrays, which bit-line arrangement places the paired bit lines side by side within the same array?
7. Compared with NOR flash, which is a characteristic of NAND flash memory?
8. What is a typical use of NOR flash memory?
9. In an SRAM read, what is the operation called that charges the bit lines in advance to the supply voltage or similar?
10. In a 6T SRAM cell, which design is needed so that the cell contents are not flipped during a read (to prevent read upset)?
11. Which is an example of a "write assist" technique to prevent SRAM write failures at low voltage?
12. Which correctly describes reading in capacitor-type FeRAM?

Related terms

Sense amplifier Word line CMOS Mobility Refresh Precharge NAND flash memory NOR flash memory Microcontroller 6T SRAM cell