HDL & Verification

What is the role of a lint tool in HDL verification?

  1. AA device that removes lint from chips
  2. BA tool for displaying simulation waveforms attractively
  3. CExamining code without simulation to find problems such as width mismatches, unintended latches and unsynthesizable constructs
Show answer and explanation

Answer: C. Examining code without simulation to find problems such as width mismatches, unintended latches and unsynthesizable constructs

A lint tool statically checks HDL code against rules and flags constructs that are legal but prone to problems, such as assignments between different widths, incomplete sensitivity lists, inferred latches, mixed blocking and nonblocking assignments and clocking mistakes. It runs without any tests, so using it from early in design reduces later verification effort.

  • A. It is not a physical cleaning device.
  • B. It is not a waveform viewer.
  • C. Correct. It finds mistakes early and cheaply.
Practice this topic Back to topic

More HDL & Verification questions

  1. What is the main purpose of simulating the post-synthesis or post-layout gate-level netlist with delay information?
  2. What is a structure like the code above, where a combinational output feeds back to its own input without passing through a flip-flop, called, and why should it be avoided?
  3. When the code above is synthesized for an FPGA, how is it generally implemented?
  4. In combinational logic, how does a long if/else-if chain compare with a case statement whose conditions are mutually exclusive?
  5. What is the difference between Verilog's equality operators "==" and "==="?