HDL & Verification

Intending combinational logic, someone wrote the code above. What problem can occur?

always @(a)
    y = a & b;
  1. Ab is removed from the circuit and y becomes equal to a
  2. BSynthesis fails and no circuit is produced
  3. CWhen only b changes, simulation does not update y, so it disagrees with the synthesized circuit, where y follows b
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Answer: C. When only b changes, simulation does not update y, so it disagrees with the synthesized circuit, where y follows b

A simulator runs the block only when a signal in the sensitivity list changes, so when only b changes, y keeps its stale value. Logic synthesis, however, ignores the list and builds an AND gate from the block's contents, so in the real circuit changes in b do reach y. This is dangerous: simulation looks right while the hardware behaves differently. Writing "@(*)" prevents it.

  • A. Synthesis builds an AND gate.
  • B. Most synthesis tools warn but still build the circuit.
  • C. Correct. It is the classic sensitivity-list omission.
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More HDL & Verification questions

  1. Intending combinational logic, someone writes the code above. What does logic synthesis produce?
  2. Why does the code above create a latch, and what is the fix?
  3. Which coding style is commonly used to prevent unintended latches in combinational always blocks?
  4. Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?
  5. When the code above, which counts the 1s in 8-bit d, is synthesized, what kind of circuit results?