HDL & Verification

In circuits using asynchronous reset, why is reset release (the 0-to-1 transition) synchronized to the clock through two flip-flops before distribution?

  1. ATo delay asserting reset by two clocks for safety
  2. BTo make the reset signal twice as fast
  3. CIf release lands near a clock edge, flip-flops may leave reset on different cycles or become unstable, so release is aligned to the clock
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Answer: C. If release lands near a clock edge, flip-flops may leave reset on different cycles or become unstable, so release is aligned to the clock

If an asynchronous reset is released just before or after a clock edge, the timing requirements for release are violated, and one flip-flop may start in this cycle while another starts in the next. This can start a state machine in an illegal state. A reset synchronizer applies reset immediately but aligns only its release to the clock through two flip-flops before distributing it.

  • A. Assertion still takes effect immediately.
  • B. It does not change speed.
  • C. Correct. Assertion is asynchronous; release is synchronous.
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