HDL & Verification

What circuit does the Verilog assign statement above represent?

assign y = (a & b) | c;
  1. ACombinational logic ORing c with the AND of a and b; y changes immediately when inputs change
  2. BA flip-flop that updates y on every clock
  3. CA circuit that computes once and never changes afterward
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Answer: A. Combinational logic ORing c with the AND of a and b; y changes immediately when inputs change

An assign statement, called a continuous assignment, represents wiring in which the value of the right-hand expression is always reflected on the left-hand signal. If any input on the right changes, the output y changes right away (after gate delay). This example becomes combinational logic made of an AND gate and an OR gate. It has no memory, so holding a value requires an always block updated by a clock.

  • A. Correct. It is called a continuous assignment.
  • B. No clock is involved.
  • C. The output follows every input change.
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More HDL & Verification questions

  1. What circuit does logic synthesis create from the Verilog above?
  2. How does Verilog's nonblocking assignment (<=) behave?
  3. In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
  4. Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?
  5. What is the common guideline for choosing assignment types in Verilog?