HDL & Verification

When the code above is synthesized for an FPGA, how is it generally implemented?

reg [7:0] mem [0:255];
always @(posedge clk) begin
    if (we) mem[addr] <= din;
    dout <= mem[addr];
end
  1. AIt cannot be synthesized and causes an error
  2. BIt becomes 256 independent adders
  3. CIt is inferred as an 8-bit × 256-word memory and mapped to the FPGA's built-in block RAM
Show answer and explanation

Answer: C. It is inferred as an 8-bit × 256-word memory and mapped to the FPGA's built-in block RAM

When a reg array is written and read synchronously with the clock in a standard pattern, synthesis tools recognize (infer) it as memory and map it to FPGA block RAM or ASIC memory macros. Making the read synchronous too is the key to matching block RAM; an asynchronous read may instead be built from many flip-flops or a different kind of memory.

  • A. A reg array can be synthesized as memory.
  • B. No addition is involved.
  • C. Correct. Written in a standard pattern, it is recognized as memory.
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