HDL & Verification

In the code above, when sel is X, Verilog simulation selects b for y. Why is this a problem for verification?

always @(*)
    if (sel) y = a;
    else     y = b;
  1. Ay always becomes X and simulation stops
  2. BThe real chip also always selects b when sel is X
  3. CX is treated as false and a definite value b appears, so the bug of an unknown sel is hidden in simulation
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Answer: C. X is treated as false and a definite value b appears, so the bug of an unknown sel is hidden in simulation

A Verilog if statement treats an X condition as false and executes the else branch. So y gets the definite value b, and the bug of an unknown sel is hidden in simulation. In the real circuit sel is either 0 or 1, and a may be selected. This is called X-optimism and is countered by coding styles that propagate X or by adding assertions that detect X.

  • A. y does not become X; it becomes b.
  • B. In the real chip either a or b could be selected.
  • C. Correct. This is known as X-optimism.
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