HDL & Verification
When the code above, which counts the 1s in 8-bit d, is synthesized, what kind of circuit results?
always @(*) begin
count = 0;
for (i = 0; i < 8; i = i + 1)
count = count + d[i];
end- AA sequential circuit counting one bit per clock over 8 cycles
- BThe loop is unrolled into eight steps, giving combinational logic with a chain of adders
- CFor loops cannot be synthesized, so it errors out
Show answer and explanation
Answer: B. The loop is unrolled into eight steps, giving combinational logic with a chain of adders
An HDL for loop does not reuse the same circuit repeatedly as software would; synthesis unrolls it into as many copies as there are iterations. Here it becomes combinational logic with eight adders in a row, computing everything within one clock. Many iterations make the circuit large and slow, so care is needed. To compute over time with less hardware, write a clocked state machine instead.
- A. No clock is used, so it does not count over time.
- B. Correct. The fixed iteration count allows unrolling.
- C. For loops with fixed bounds are synthesizable.