HDL & Verification

What is the period of the clock generated by the testbench code above (time unit 1 ns)?

initial clk = 0;
always #5 clk = ~clk;
  1. A5 ns
  2. B20 ns
  3. C10 ns
Show answer and explanation

Answer: C. 10 ns

"always #5 clk = ~clk;" keeps toggling clk every 5 time units. Two toggles, 0 to 1 and 1 to 0, make one period, so the period is 10 ns and the frequency 100 MHz. This is how testbenches generate clocks. Real circuit clocks come from oscillators or PLLs, so this code never becomes hardware.

  • A. 5 ns is half a period.
  • B. That counts four toggle intervals.
  • C. Correct. It toggles every 5 ns, so one period is 10 ns.
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