HDL & Verification

What is the common guideline for choosing assignment types in Verilog?

  1. AUse only blocking assignment (=) everywhere
  2. BUse nonblocking (<=) for clocked sequential logic and blocking (=) in combinational always blocks
  3. CMix both arbitrarily in the same always block
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Answer: B. Use nonblocking (<=) for clocked sequential logic and blocking (=) in combinational always blocks

Writing sequential logic with nonblocking assignments matches hardware where all flip-flops capture values simultaneously, so results do not depend on statement order or on the execution order of other always blocks. Combinational logic naturally computes intermediate values from top to bottom, so blocking assignments are used there. It is also important not to mix the two within one always block.

  • A. Blocking in sequential logic often yields unintended circuits.
  • B. Correct. It keeps simulation and hardware behavior consistent.
  • C. Mixing makes behavior hard to follow and error-prone.
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  4. Why does the code above create a latch, and what is the fix?
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