HDL & Verification

What is the basic structure of a state machine written in an HDL?

  1. AOnly memory to remember the state, with no logic
  2. BOnly output logic, with no memory of state
  3. CA register holding the current state, combinational logic choosing the next state, and combinational logic producing outputs
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Answer: C. A register holding the current state, combinational logic choosing the next state, and combinational logic producing outputs

A state machine keeps the current state in a flip-flop register, determines the next state from the current state and inputs with combinational logic, and updates the state at the clock edge. Outputs are produced from the current state (and inputs) by combinational logic. Many circuits that follow a procedure, such as protocol controllers, vending machines and traffic lights, are written as state machines.

  • A. Logic to determine the next state is needed.
  • B. A state register is required.
  • C. Correct. The state is updated by the clock.
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More HDL & Verification questions

  1. In the state machine above, why does the second always block begin with "next = state;"?
  2. What characterizes a Mealy state machine?
  3. What is a characteristic of one-hot encoding for state machine states?
  4. For a state machine with three states, how many flip-flops are needed to store the state (binary encoding / one-hot encoding)?
  5. In the 4-bit counter above, when count is 15 and a rising clock edge arrives, what does count become?