HDL & Verification

In the 4-bit counter above, when count is 15 and a rising clock edge arrives, what does count become?

reg [3:0] count;
always @(posedge clk)
    count <= count + 1;
  1. A16
  2. B0
  3. CIt stays at 15
Show answer and explanation

Answer: B. 0

A 4-bit reg can represent only 0 to 15. Adding 1 to 15 (1111 in binary) gives 10000, but the top bit does not fit and is dropped, so count returns to 0000, that is, 0. This property is used to build counters that repeat every fixed number of steps. Unintended overflow, however, causes bugs, so signal bit widths always deserve attention.

  • A. The 4-bit range is 0 to 15.
  • B. Correct. Four bits cannot hold 16, so it wraps to 0.
  • C. The addition happens and wraps to 0.
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