HDL & Verification
In a testbench, changing a design input with a blocking assignment at the same instant as the rising clock edge can cause problems. Which pairs the reason with a fix correctly?
- AWhether the design captures the old or new value depends on execution order (a race); change inputs away from the clock edge or with nonblocking assignments
- BThe clock frequency automatically drops; make the clock faster
- CBlocking assignments are not allowed in testbenches; use assign everywhere
Show answer and explanation
Answer: A. Whether the design captures the old or new value depends on execution order (a race); change inputs away from the clock edge or with nonblocking assignments
When the testbench updates an input at the same instant the design's flip-flops sample it, the captured value can be old or new depending on which the simulator executes first. This is a simulation race, and results may even differ between simulators. It is prevented by changing inputs on the falling edge or slightly after the edge, or by using nonblocking assignments or SystemVerilog clocking blocks.
- A. Correct. It avoids a simulation race.
- B. The frequency does not change.
- C. Blocking assignments are allowed in testbenches.