HDL & Verification

In the state machine above, why does the second always block begin with "next = state;"?

always @(posedge clk)
    state <= next;
always @(*) begin
    next = state;
    case (state)
        IDLE: if (start) next = RUN;
        RUN:  if (done)  next = IDLE;
    endcase
end

ATo stay in the current state when no condition matches and to assign next in every case, preventing a latch
BTo return the state to IDLE every time
CTo stop the clock

Show answer and explanation

Answer: A. To stay in the current state when no condition matches and to assign next in every case, preventing a latch

Splitting a state machine into a register block that updates the state and a combinational block that computes the next state is a common style. In the combinational block, if nothing assigns next when start or done is 0, a latch forms. Starting with "next = state;" clearly expresses staying in the current state when no condition matches, while preventing the latch.

A. Correct. It sets the default value first.
B. It holds the current state rather than resetting to IDLE.
C. It has nothing to do with the clock.

In the state machine above, why does the second always block begin with "next = state;"?

More HDL & Verification questions