HDL & Verification
What does the generate statement above do?
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin : g
fifo u_fifo (.clk(clk), .din(din[i]), .dout(dout[i]));
end
endgenerate- AIt reuses one fifo four times over four clocks
- BIt displays the fifo four times only during simulation
- CIt creates four instances of the fifo module, each connected to a different element of din and dout
Show answer and explanation
Answer: C. It creates four instances of the fifo module, each connected to a different element of din and dout
A for loop inside a generate block expands its contents for each genvar value, replicating hardware descriptions. Here four fifo instances, g[0].u_fifo through g[3].u_fifo, are created, each connected to din[i] and dout[i]. Making the channel or bit count a parameter lets the number of instances change accordingly, so regularly structured circuits can be written concisely.
- A. It does not reuse; four circuits are placed side by side.
- B. It creates hardware, not display output.
- C. Correct. It is expanded into four circuits at synthesis.