HDL & Verification

What is the difference between synchronous and asynchronous resets?

  1. AA synchronous reset acts regardless of the clock; an asynchronous one only at clock edges
  2. BA synchronous reset takes effect only at clock edges; an asynchronous reset takes effect immediately regardless of the clock
  3. CThey behave identically; only the names differ
Show answer and explanation

Answer: B. A synchronous reset takes effect only at clock edges; an asynchronous reset takes effect immediately regardless of the clock

A synchronous reset samples the reset signal at clock edges like any other input, which eases timing analysis, but it cannot reset without a running clock. An asynchronous reset uses the flip-flop's reset pin directly, so it acts at once even without a clock, but if release happens near a clock edge, flip-flops may come out of reset at different cycles.

  • A. It is the other way around.
  • B. Correct. Each has advantages and caveats.
  • C. They differ in when the reset takes effect.
Practice this topic Back to topic

More HDL & Verification questions

  1. In circuits using asynchronous reset, why is reset release (the 0-to-1 transition) synchronized to the clock through two flip-flops before distribution?
  2. What is the basic structure of a state machine written in an HDL?
  3. In the state machine above, why does the second always block begin with "next = state;"?
  4. What characterizes a Mealy state machine?
  5. What is a characteristic of one-hot encoding for state machine states?