HDL & Verification
always @(*) begin
sum = sum + in;
endThe code above was written intending an accumulator that keeps adding the input in. Which pair correctly states the problem with this code and how to fix it?
- AThere is no problem; it synthesizes a circuit that adds in to sum once each time in changes
- BA signal is missing from the sensitivity list, so simulation and synthesis disagree; rewrite it as @(in)
- CThe adder output feeds back to its own input without passing through a flip-flop, so the value never settles; write sum <= sum + in; inside always @(posedge clk) to add once per clock
Show answer and explanation
Answer: C. The adder output feeds back to its own input without passing through a flip-flop, so the value never settles; write sum <= sum + in; inside always @(posedge clk) to add once per clock
always @(*) describes combinational logic, so this code becomes a circuit in which an adder that takes sum as an input drives sum directly with its output. With no flip-flop, every change at the adder output changes its input, and the value keeps circulating without settling: a combinational loop. Static timing analysis cannot handle it, and many lint and synthesis tools issue warnings or errors. A circuit that accumulates values needs a flip-flop that updates the value once per rising clock edge: use a nonblocking assignment inside always @(posedge clk), and set the initial value with a reset.
- A. Without a clock, nothing delimits each "once," so it does not become an accumulator.
- B. @(*) automatically includes sum and in, which are read, so nothing is missing. The loop remains even with @(in).
- C. Correct. A flip-flop is inserted in the feedback path.