HDL & Verification

Which set of values makes up the four-state logic used in Verilog simulation?

  1. A0, 1, X (unknown) and Z (high impedance)
  2. B0, 1, 2 and 3
  3. CTrue, false, up and down
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Answer: A. 0, 1, X (unknown) and Z (high impedance)

Besides 0 and 1, Verilog signals can be X (unknown) and Z (high impedance, undriven). Uninitialized registers and signals with conflicting drivers become X, while unconnected wires and tri-state lines whose drivers are disabled become Z. Spotting X or Z in simulation is a major clue to finding bugs.

  • A. Correct. These represent real circuit conditions.
  • B. They are not the numbers 0 to 3.
  • C. Those are not logic values.
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More HDL & Verification questions

  1. In simulation, a register without reset starts as X. What happens in the real chip?
  2. In the code above, when sel is X, Verilog simulation selects b for y. Why is this a problem for verification?
  3. Which statement about tri-state descriptions that output Z (high impedance) in an HDL is generally correct?
  4. Which describes a testbench used in HDL verification?
  5. What is the period of the clock generated by the testbench code above (time unit 1 ns)?