HDL & Verification

What is the main purpose of simulating the post-synthesis or post-layout gate-level netlist with delay information?

  1. ATo run many tests faster than RTL simulation
  2. BTo check issues invisible in RTL simulation, such as initialization or reset bugs, synthesis differences and delay-related problems
  3. CTo reduce circuit area
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Answer: B. To check issues invisible in RTL simulation, such as initialization or reset bugs, synthesis differences and delay-related problems

RTL simulation is fast but cannot reveal unknown-value problems hidden by X-optimism, or cases where synthesis produced a circuit different from the description. Gate-level simulation exercises the actual gates and flip-flops, and with each gate's and wire's delay supplied in SDF format, delay-related problems also show up. It is very slow, so it is generally run on a limited set of tests.

  • A. Gate-level simulation is far slower.
  • B. Correct. Delay information is supplied in formats such as SDF.
  • C. It does not change area.
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