HDL & Verification

How does Verilog's nonblocking assignment (<=) behave?

  1. AThe left side updates immediately, and the next line sees the new value
  2. BAll right-hand sides at that time step are evaluated first, and then the left-hand sides are updated together
  3. CThe result is discarded and nothing changes
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Answer: B. All right-hand sides at that time step are evaluated first, and then the left-hand sides are updated together

With nonblocking assignment, at the clock edge every <= right-hand side is first evaluated using the old values, and only then are all left-hand sides updated together. This mirrors real hardware, where many flip-flops on the same clock capture their pre-edge inputs simultaneously. That is why nonblocking assignment is the rule for describing clocked sequential logic.

  • A. That is the behavior of blocking assignment (=).
  • B. Correct. It matches flip-flops capturing values simultaneously.
  • C. The value is updated.
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More HDL & Verification questions

  1. In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
  2. Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?
  3. What is the common guideline for choosing assignment types in Verilog?
  4. What does writing "always @(*)" mean in Verilog?
  5. Intending combinational logic, someone wrote the code above. What problem can occur?