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Blocking vs Non-Blocking Assignment in Verilog: Key Differences

Both are assignments used inside Verilog always blocks, but they differ in when the left-hand side is updated. A blocking assignment (=) updates the left-hand side as soon as the line executes, and the next line sees the new value. A non-blocking assignment (<=) first evaluates all right-hand sides at the same time step, then updates the left-hand sides together. The basic guideline is <= for clocked sequential logic and = for combinational always blocks.

AspectBlocking assignment (=)Non-blocking assignment (<=)
Syntaxa = b;a <= b;
When the left-hand side is updatedImmediately, when the line executesTogether, after all right-hand sides at the same time step have been evaluated
Value seen by the next lineThe new, updated valueThe old value before the update
Dependence on statement orderYes. Swapping lines changes the resultAlmost none. However, if the same variable is assigned twice, the later assignment wins
Corresponding hardware behaviorCombinational logic that computes intermediate values in order from top to bottomFlip-flops that all capture values at the same clock edge
Where it is mainly usedCombinational always @(*), testbench proceduresClocked sequential always @(posedge clk)
Two-stage shift register (clocked block)With q1 = d; q2 = q1; q2 also gets d at the same edge, giving only one stage of delayWith q1 <= d; q2 <= q1; q2 gets q1 from before the edge, giving two stages
Swapping values (clocked block)With a = b; b = a; a and b end up with the same valueWith a <= b; b <= a; a and b are swapped
Across multiple always blocksBlocks triggered by the same edge are prone to races where the result depends on execution orderAll right-hand sides are evaluated first, so races are unlikely
When misusedIn sequential logic, the result depends on block execution order and may differ from the synthesized circuitIn combinational logic, intermediate values are read while still stale, so simulation may differ from the synthesized circuit or blocks re-execute unnecessarily

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Blocking assignment (=)
When computing intermediate values in order inside a combinational always @(*), or writing step-by-step procedures in a testbench.
Non-blocking assignment (<=)
When describing clocked flip-flops, as in always @(posedge clk): registers, counters and state machine state updates.
Don't mix them
Do not mix = and <= inside one always block, and do not assign the same variable from multiple always blocks. In SystemVerilog, always_ff and always_comb tell the tools your intent.

FAQ

What happens if you use blocking assignments in sequential logic?

Depending on line order, a value updated at an edge passes straight to the next line, giving a circuit with fewer stages than intended. It can also cause races with other always blocks on the same clock, where the result depends on execution order, making simulation differ from the synthesized circuit.

Why does a <= b; b <= a; swap the values with non-blocking assignment?

Both right-hand sides are evaluated first using the old values, and then the left-hand sides are updated together. This behaves like two flip-flops whose outputs are connected to each other's inputs.

Which should be used in a testbench?

Blocking assignments are fine for parts that describe steps in order. However, if inputs to the circuit change at the same time as the clock edge, whether the old or new value is captured depends on execution order, so change them slightly away from the edge or use non-blocking assignments.

Check your understanding

How does Verilog's nonblocking assignment (<=) behave?

  1. AThe left side updates immediately, and the next line sees the new value
  2. BAll right-hand sides at that time step are evaluated first, and then the left-hand sides are updated together
  3. CThe result is discarded and nothing changes
Show answer and explanation

Answer: B. All right-hand sides at that time step are evaluated first, and then the left-hand sides are updated together

With nonblocking assignment, at the clock edge every <= right-hand side is first evaluated using the old values, and only then are all left-hand sides updated together. This mirrors real hardware, where many flip-flops on the same clock capture their pre-edge inputs simultaneously. That is why nonblocking assignment is the rule for describing clocked sequential logic.

What is the common guideline for choosing assignment types in Verilog?

  1. AUse only blocking assignment (=) everywhere
  2. BUse nonblocking (<=) for clocked sequential logic and blocking (=) in combinational always blocks
  3. CMix both arbitrarily in the same always block
Show answer and explanation

Answer: B. Use nonblocking (<=) for clocked sequential logic and blocking (=) in combinational always blocks

Writing sequential logic with nonblocking assignments matches hardware where all flip-flops capture values simultaneously, so results do not depend on statement order or on the execution order of other always blocks. Combinational logic naturally computes intermediate values from top to bottom, so blocking assignments are used there. It is also important not to mix the two within one always block.

In a testbench, changing a design input with a blocking assignment at the same instant as the rising clock edge can cause problems. Which pairs the reason with a fix correctly?

  1. AWhether the design captures the old or new value depends on execution order (a race); change inputs away from the clock edge or with nonblocking assignments
  2. BThe clock frequency automatically drops; make the clock faster
  3. CBlocking assignments are not allowed in testbenches; use assign everywhere
Show answer and explanation

Answer: A. Whether the design captures the old or new value depends on execution order (a race); change inputs away from the clock edge or with nonblocking assignments

When the testbench updates an input at the same instant the design's flip-flops sample it, the captured value can be old or new depending on which the simulator executes first. This is a simulation race, and results may even differ between simulators. It is prevented by changing inputs on the falling edge or slightly after the edge, or by using nonblocking assignments or SystemVerilog clocking blocks.

  1. In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
  2. Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?
  3. Intending combinational logic, someone wrote the code above. What problem can occur?

Practice HDL & Verification questions

Key terms explained

Blocking assignment
Verilog's "=" assignment, which updates the left side immediately so the next statement sees the new value. Used in combinational always blocks and testbenches.
Nonblocking assignment
Verilog's "<=" assignment, which evaluates every right-hand side at a time step before updating all left-hand sides together. It matches flip-flop behavior and is used for sequential logic.
Sensitivity list
The list in @( ) after a Verilog always that names the signals triggering the block. Omissions in combinational logic make simulation and hardware disagree.
Verilog
A hardware description language widely used for digital design and verification, describing circuits as modules with behavior expressed through assign and always.

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