HDL & Verification

What is a structure like the code above, where a combinational output feeds back to its own input without passing through a flip-flop, called, and why should it be avoided?

assign a = b & c;
assign b = a | d;
  1. AIt is a combinational loop; it can oscillate or never settle, and timing analysis becomes impossible
  2. BIt is a pipeline, and the circuit becomes too fast
  3. CIt is a shift register, and data is lost
Show answer and explanation

Answer: A. It is a combinational loop; it can oscillate or never settle, and timing analysis becomes impossible

With a determining b and b determining a and no flip-flop in between, values can circulate with every gate delay and oscillate, or settle to whatever the delay differences dictate. Latch-like memory can also form unintentionally. Static timing analysis cannot handle paths that form a loop. When feedback is needed, a flip-flop must be inserted so the value updates once per clock.

  • A. Correct. Many tools issue errors or warnings.
  • B. A pipeline is divided by flip-flops.
  • C. A shift register is built from flip-flops.
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