HDL & Verification

In combinational logic, how does a long if/else-if chain compare with a case statement whose conditions are mutually exclusive?

  1. AAn if/else-if chain implies priority on earlier conditions and tends to be deep and slow, while a case tends to become parallel selection
  2. BBoth styles always synthesize to exactly the same circuit
  3. Ccase cannot be synthesized; only if can
Show answer and explanation

Answer: A. An if/else-if chain implies priority on earlier conditions and tends to be deep and slow, while a case tends to become parallel selection

An if/else-if chain means "if the first condition holds take it, otherwise check the next", implying a priority circuit like a priority encoder, with one multiplexer per condition in series and long delay. A case selecting on mutually exclusive values tends to become a parallel structure like a single large multiplexer and is faster. Modern synthesis tools, however, often optimize either form.

  • A. Correct. The difference is whether conditions have priority.
  • B. Circuits can differ depending on priority.
  • C. case is synthesizable too.
Practice this topic Back to topic

More HDL & Verification questions

  1. What is the difference between Verilog's equality operators "==" and "==="?
  2. What is a major difference between a description written in an HDL such as Verilog and a software program in a language such as C?
  3. What is the purpose of a module in Verilog?
  4. What is the difference between wire and reg in Verilog?
  5. What circuit does the Verilog assign statement above represent?