HDL & Verification

In Verilog, two 8-bit signals a and b are added and assigned to an 8-bit signal s (assign s = a + b;). What should be watched for?

  1. AAdding two 8-bit values cannot be written in Verilog
  2. BThe result is automatically widened to 16 bits
  3. CIf the sum exceeds 255, the ninth-bit carry is discarded, so make s 9 bits if the carry is needed
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Answer: C. If the sum exceeds 255, the ninth-bit carry is discarded, so make s 9 bits if the carry is needed

The sum of two 8-bit values can reach 255 + 255 = 510, which needs 9 bits. If s is 8 bits, the carry is silently dropped, and 200 + 100 becomes 44, for example. To keep the carry, declare s as 9 bits. Verilog does not reject assignments between different widths but truncates or extends them, so checking width mismatches with a lint tool is effective.

  • A. It can be written normally.
  • B. An 8-bit destination truncates it to 8 bits.
  • C. Correct. The result is truncated to the destination width.
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