HDL & Verification

Which coding style is commonly used to prevent unintended latches in combinational always blocks?

  1. AWrite as many branches as possible and omit else
  2. BAssign default values to every output signal at the top of the block before the conditional logic
  3. CDeclare all outputs as wire and assign them inside always
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Answer: B. Assign default values to every output signal at the top of the block before the conditional logic

Putting defaults such as "y = 0; valid = 0;" at the top ensures every output is assigned at least its default on whatever path the later branches take, so nothing needs to hold its value and no latch forms. This is especially helpful for state machine outputs with many conditions. With SystemVerilog's always_comb, tools also warn if a latch is inferred.

  • A. Omitting else causes latches.
  • B. Correct. Every path then assigns a value.
  • C. A wire cannot be assigned in an always block.
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  1. Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?
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