HDL & Verification

What is the difference between Verilog's equality operators "==" and "==="?

  1. A== yields X if X or Z is involved, while === compares X and Z literally as values and always yields 0 or 1
  2. B== and === behave identically
  3. C=== compares three values at once
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Answer: A. == yields X if X or Z is involved, while === compares X and Z literally as values and always yields 0 or 1

== behaves like a hardware comparator, so if either operand contains an X or Z bit, the result is X (unknown). === is called case equality and compares X as X and Z as Z literally, so a testbench can use it to check whether an output has become X. Real circuits cannot distinguish X or Z, so === is not synthesizable and is a testbench-only operator.

  • A. Correct. === is used mainly in testbenches.
  • B. They treat X and Z differently.
  • C. It compares two values.
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