HDL & Verification

What is the advantage of using SystemVerilog's always_ff and always_comb instead of Verilog's always?

  1. Aalways_ff always doubles circuit speed
  2. Balways_comb makes simulation unnecessary
  3. CTools know the designer's intent (flip-flops or combinational logic) and can warn when the result differs, for example a latch
Show answer and explanation

Answer: C. Tools know the designer's intent (flip-flops or combinational logic) and can warn when the result differs, for example a latch

Verilog's always can describe flip-flops, combinational logic or latches, so tools do not know the designer's intent. Writing always_ff declares flip-flops and always_comb declares combinational logic, so tools can issue warnings or errors when, for example, an incomplete condition infers a latch. always_comb also derives its sensitivity automatically from the signals it reads.

  • A. It has nothing to do with speed.
  • B. Simulation is still needed.
  • C. Correct. always_comb also determines its sensitivity list automatically.
Practice this topic Back to topic

More HDL & Verification questions

  1. What is the advantage of writing a module with a parameter as above?
  2. What does the generate statement above do?
  3. What is the role of a lint tool in HDL verification?
  4. What is the main purpose of simulating the post-synthesis or post-layout gate-level netlist with delay information?
  5. What is a structure like the code above, where a combinational output feeds back to its own input without passing through a flip-flop, called, and why should it be avoided?