HDL & Verification

Which describes a testbench used in HDL verification?

  1. AFactory equipment for manufacturing circuits
  2. BA simulation-only description that drives inputs to the circuit under test and checks whether outputs are correct; it is not synthesized
  3. CAn instrument for measuring circuit power
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Answer: B. A simulation-only description that drives inputs to the circuit under test and checks whether outputs are correct; it is not synthesized

A testbench is HDL code that instantiates the design under test (DUT), generates clocks, resets and input signals, and observes outputs. Because it is never synthesized, it can freely use simulation-only features such as delays, file I/O and display statements. It sometimes takes as much effort as the design itself, or more.

  • A. It is not factory equipment.
  • B. Correct. It is a test environment wrapped around the design.
  • C. It is a simulation description, not a physical instrument.
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More HDL & Verification questions

  1. What is the period of the clock generated by the testbench code above (time unit 1 ns)?
  2. In a testbench, changing a design input with a blocking assignment at the same instant as the rising clock edge can cause problems. Which pairs the reason with a fix correctly?
  3. What characterizes a self-checking testbench?
  4. What is the purpose of a reference (golden) model written in C or similar in verification?
  5. What is the main purpose of dumping simulation results to a file in a format such as VCD?