HDL & Verification

What does writing "always @(*)" mean in Verilog?

  1. AIt describes a flip-flop that runs on every rising clock edge
  2. BIt runs only once at the start of simulation
  3. CIt runs whenever any signal read inside the block changes, describing combinational logic
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Answer: C. It runs whenever any signal read inside the block changes, describing combinational logic

The list inside @( ) after always is called the sensitivity list and specifies which signal changes trigger the block. Writing "*" automatically includes every signal read in the block, correctly describing combinational logic. Listing signals by hand invites omissions, so "@(*)" or SystemVerilog's always_comb is the safe choice for combinational logic.

  • A. Clock edges are specified with posedge and similar.
  • B. Running once is what initial does.
  • C. Correct. It is like listing every signal read automatically.
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More HDL & Verification questions

  1. Intending combinational logic, someone wrote the code above. What problem can occur?
  2. Intending combinational logic, someone writes the code above. What does logic synthesis produce?
  3. Why does the code above create a latch, and what is the fix?
  4. Which coding style is commonly used to prevent unintended latches in combinational always blocks?
  5. Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?