HDL & Verification

Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?

  1. AAn assign statement
  2. Balways @(posedge clk)
  3. CA delay specification such as #10
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Answer: C. A delay specification such as #10

"#10" advances simulation time by 10 units, but logic synthesis cannot build delays, so it ignores them. Real circuit delays are set by the gates and wiring used. Testbench constructs such as $display and file I/O likewise do not become hardware. Mixing such constructs into synthesizable RTL causes simulation and hardware behavior to diverge.

  • A. An assign statement becomes combinational logic.
  • B. This becomes flip-flops.
  • C. Correct. Delays are determined by the placed-and-routed circuit.
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