For a single flip-flop to flip-flop path, this calculator applies the same reasoning as static timing analysis (STA) to find the setup and hold slack. Change the delays and skew to see which check fails first. All values are in nanoseconds.
Results
Setup slack
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Hold slack
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Maximum frequency
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Met Violated
The top row checks that the latest data arrives before the setup deadline (dashed line); the bottom row checks that the earliest data arrives after the hold deadline. Negative slack means a violation.
See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
The setup check
The latest time new data can reach the capturing flip-flop is the maximum clock-to-Q delay plus the maximum combinational delay. It must arrive before the next capture edge (period plus skew) minus the setup time and clock uncertainty. Setup slack is the deadline minus the arrival time; if it is negative the period is too short, so you must lower the frequency or shorten the logic.
The hold check
Hold asks whether data launched on the same clock edge arrives so quickly that it corrupts the value the capturing flip-flop is still latching. The earliest arrival, the minimum clock-to-Q delay plus the minimum combinational delay, must come after the skew plus the hold time. The clock period does not appear in the hold check, so slowing the clock never fixes a hold violation; tools insert delay buffers on the short path instead.
How skew shifts both checks
When the capture clock arrives later than the launch clock (positive skew), the setup deadline moves out, which helps setup but hurts hold. Negative skew does the opposite. Designers sometimes add skew on purpose to rescue a critical setup path (useful skew), but must re-check hold. Real STA checks every path at its worst case: setup at the slow corner and hold at the fast corner.
Maximum frequency
The period at which setup slack is exactly zero is the minimum period for the path, and its inverse is the maximum frequency: fmax = 1 / (clock-to-Q + combinational delay + setup + uncertainty − skew). A chip's maximum frequency is set by its slowest path, the critical path. Adding pipeline stages shortens the logic per stage and raises the achievable frequency.
AThe minimum time data must be held after the clock edge
BThe minimum time the data input must be stable before the clock edge
CThe time from power-on until it starts operating
Show answer and explanation
Answer: B. The minimum time the data input must be stable before the clock edge
For a flip-flop to capture correctly, data must be stable for a certain time before the clock edge—the setup time. A violation occurs if the data-path delay exceeds the clock period minus the setup time, and it can be fixed by slowing the clock. The time data must remain stable after the edge is the hold time. Violating either can capture wrong values or cause metastability.
AThe time the data input must be stable before the active clock edge
BThe time from the clock edge until the output changes
CThe time the data input must remain unchanged after the active clock edge
Show answer and explanation
Answer: C. The time the data input must remain unchanged after the active clock edge
Hold time is the minimum time data must stay stable after the clock edge. If the path from one flip-flop to the next is too short, new data launched by the same edge arrives too early and violates hold. Because it does not depend on the clock period, slowing the clock cannot fix it; the remedy is inserting buffers to add delay. A hold violation found after manufacturing can render the chip unusable, so design-time verification is critical.
FAQ
How do you fix setup and hold violations differently?
Setup violations are fixed by lowering the clock frequency, speeding up or restructuring the logic, or adding pipeline stages. Hold violations do not depend on frequency, so they are fixed by adding buffers to increase delay on the short path.
Does clock skew affect setup or hold?
Both, in opposite directions. Positive skew, where the capture clock arrives later, helps setup and hurts hold; negative skew does the reverse.
What is slack in timing analysis?
Slack is the timing margin: the required time minus the actual arrival time. Positive slack means the check passes; negative slack is a violation.