HDL & Verification
What type of reset does the code above have, and how does it behave?
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0;
else q <= d;- AA synchronous reset: q becomes 0 only at a rising clock edge while rst_n is 0
- BAn asynchronous reset: when rst_n goes to 0, q becomes 0 immediately without waiting for a clock
- Cq becomes 0 when rst_n goes to 1
Show answer and explanation
Answer: B. An asynchronous reset: when rst_n goes to 0, q becomes 0 immediately without waiting for a clock
Because "negedge rst_n" is in the sensitivity list, the block also runs the instant rst_n falls from 1 to 0, and q becomes 0 regardless of the clock. This is an asynchronous reset. The "_n" suffix is a convention for active-low signals. It can reset even when the clock is stopped, but the timing of reset release needs care.
- A. The reset edge is also a trigger, so it is not synchronous.
- B. Correct. The reset edge is in the sensitivity list.
- C. _n indicates active-low.