HDL & Verification

Intending a to be signed -1, someone wrote the code above, and gt became 1. Why?

wire [7:0] a = 8'hFF;
wire gt = (a > 8'd1);
  1. AWithout a signed declaration, a was compared as unsigned 255
  2. BComparisons in Verilog always return 1
  3. C8'hFF equals 0
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Answer: A. Without a signed declaration, a was compared as unsigned 255

Verilog treats signals as unsigned unless declared signed, so 8'hFF is 255, and 255 > 1 is true. Declaring the signals as "wire signed [7:0]" compares a as two's-complement -1, giving 0. There is also a rule that if any operand in an expression is unsigned, the whole expression is evaluated unsigned, so signed arithmetic requires keeping all operand types consistent.

  • A. Correct. Signed treatment requires a signed declaration.
  • B. Comparisons yield 0 or 1 depending on the values.
  • C. 8'hFF is 255 (or -1 if signed).
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