HDL & Verification

What is a major difference between a description written in an HDL such as Verilog and a software program in a language such as C?

  1. AAn HDL description represents circuits that operate concurrently
  2. BAn HDL description is a sequence of instructions executed one line at a time from the top
  3. CHDLs cannot use variables or conditional branches
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Answer: A. An HDL description represents circuits that operate concurrently

An HDL looks like a program, but logic synthesis turns what is written into gates and flip-flops. Every part of a circuit operates at all times, so multiple assign statements and always blocks work in parallel regardless of their order in the text. Thinking "do this, then that" as in software leads to unintended circuits, so it is important to picture the circuit being created while writing.

  • A. Correct. Every part of the circuit is always operating at once.
  • B. That is the software way of thinking.
  • C. HDLs do use signals and conditional branches.
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More HDL & Verification questions

  1. What is the purpose of a module in Verilog?
  2. What is the difference between wire and reg in Verilog?
  3. What circuit does the Verilog assign statement above represent?
  4. What circuit does logic synthesis create from the Verilog above?
  5. How does Verilog's nonblocking assignment (<=) behave?