HDL & Verification

What circuit does logic synthesis create from the Verilog above?

always @(posedge clk)
    q <= d;
  1. AAn AND gate of d and clk
  2. BA D flip-flop that captures d on the rising clock edge
  3. CA latch that passes d whenever clk is 1
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Answer: B. A D flip-flop that captures d on the rising clock edge

"always @(posedge clk)" means the assignments inside happen only at the instant of the rising clock edge, and synthesis turns this into an edge-triggered flip-flop. q holds the value d had at the rising edge until the next one. Almost all storage in synchronous circuits is written this way. It must be distinguished from a latch, which responds to clock level rather than edges.

  • A. The clock serves as an edge trigger; no AND is built.
  • B. Correct. posedge means the rising edge.
  • C. It is edge-triggered, so it is not a latch.
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More HDL & Verification questions

  1. How does Verilog's nonblocking assignment (<=) behave?
  2. In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
  3. Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?
  4. What is the common guideline for choosing assignment types in Verilog?
  5. What does writing "always @(*)" mean in Verilog?