HDL & Verification

Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?

always @(posedge clk) begin
    q1 = d;
    q2 = q1;
end
  1. Aq2 receives q1 updated at the same edge (that is, d), so the circuit delays by only one stage
  2. Bq1 and q2 stay 0 forever
  3. CIt correctly becomes a two-stage shift register with no problem
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Answer: A. q2 receives q1 updated at the same edge (that is, d), so the circuit delays by only one stage

With blocking assignment, line 1 immediately updates q1 to d, and line 2 gives q2 the updated q1, which is d. So q2 equals q1, and both simulation and the synthesized circuit delay by only one stage. Writing "q1 <= d; q2 <= q1;" gives q2 the pre-edge q1, yielding the intended two-stage shift register. Reversing the lines might also work, but that invites mistakes.

  • A. Correct. Writing it with <= gives two stages.
  • B. The values do update.
  • C. With blocking assignment, the next line uses the new value.
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