HDL & Verification

Which describes constrained random verification in SystemVerilog?

  1. AInput values are generated randomly within constraints allowed by the specification, broadly exercising cases people might not think of
  2. BInput values are generated completely at random, including many values outside the specification
  3. CPeople write every input value by hand
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Answer: A. Input values are generated randomly within constraints allowed by the specification, broadly exercising cases people might not think of

Tests people devise (directed tests) tend to miss bugs in combinations the designer did not anticipate. Constrained random verification states constraints such as "addresses are multiples of 4" or "length is 1 to 256" and generates random inputs within them, exercising many cases with only meaningful inputs. Coverage measures which cases were hit, and gaps are filled by adjusting constraints or adding directed tests.

  • A. Correct. It is combined with coverage measurement.
  • B. Mostly out-of-spec inputs make for meaningless verification.
  • C. That is directed testing.
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