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Mealy vs Moore Machine: Outputs, Timing and State Count

A state machine consists of a register that holds the current state, combinational logic that decides the next state and combinational logic that decides the outputs. Mealy and Moore machines differ in what determines the outputs. In a Mealy machine, the outputs depend on both the current state and the current inputs, so an input change shows up at the output within the same cycle. In a Moore machine, the outputs depend only on the current state, so an input change reaches the output only after the clock updates the state, one cycle later. Mealy machines need fewer states and respond faster; Moore machines give stable outputs and more predictable timing.

AspectMealy machineMoore machine
What determines the outputCurrent state and current inputsCurrent state only
Output in a state diagramWritten on the transition arrows as "input/output"Written inside the state circle with the state name
Response to inputsWhen an input changes, the output changes within the same cycle without waiting for the clockThe output changes after the next clock updates the state, one cycle later than a Mealy machine
State count (overlapping "101" detector)3 states (no match, matched 1, matched 10)4 states (an extra "101 detected" state is needed to output 1)
State count (in general)Equal to or fewer than a Moore machine for the same behaviorMealy states must be split by the output of their incoming transitions, so it tends to need more
Glitches and noiseInput glitches and noise pass through the combinational logic straight to the outputInput noise does not reach the output; encoding states so outputs come directly from state-register bits also removes output glitches
Timing pathsCombinational logic connects inputs to outputs, lengthening paths that include surrounding logic; connecting Mealy machines together can create combinational loopsOutputs depend only on the state after the clock edge, so paths are broken by registers and timing is easier to analyze
HDL styleThe combinational output block reads the inputs as well as the stateOutput expressions read only the state (for example, a case statement setting outputs per state); outputs are often driven from registers
Where it fitsControl that must respond with no cycle of delay, or when fewer states are wantedControl signals that need clean outputs (such as signals to another clock domain or off chip), or when predictable timing matters

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Mealy machine
Suited to responding to inputs in the same cycle or keeping the state count low. Synchronize inputs to the clock first, and use the outputs where a brief glitch does no harm, for example by capturing them in flip-flops on the same clock. Registering the outputs removes glitches but adds the same one-cycle delay as a Moore machine.
Moore machine
Suited to designs that put output stability and predictable timing first. Input noise does not reach the outputs, which makes it a good fit for important control signals and signals leaving the chip. Weigh the one-cycle-later response and the tendency to need more states. Real designs often choose Mealy or Moore per output, or combine the two.

FAQ

What does "one cycle later" mean concretely?

Take a "101" detector. A Mealy machine in the "matched 10" state sets its output to 1 during the same cycle in which the input becomes 1. A Moore machine sets its output to 1 only after it captures that 1 on the clock edge and moves to the "101 detected" state, so the output is 1 in the next cycle. Both detect the same input sequences, but the Moore output is shifted one cycle later than the Mealy output.

Can Mealy and Moore machines be converted into each other?

Yes. Splitting each Mealy state by the output of the transitions entering it gives a Moore machine with the same input-output behavior, although the state count may grow and the outputs appear one cycle later. Conversely, writing each Moore state's output on the transitions entering that state gives a Mealy machine whose outputs appear one cycle earlier, and sometimes states can then be merged.

In HDL code, what makes a machine Mealy or Moore?

The output expressions. When the code is split into a block that updates the state register and a combinational block that decides the next state and outputs, the machine is Mealy if the output expressions include inputs and Moore if they depend only on the state. In the combinational block, assign every output under every condition to avoid creating unintended latches.

Does a Moore machine never glitch at its outputs?

Input changes and noise do not reach the outputs, but if combinational logic decodes the state into outputs, several state bits changing at once can cause a glitch. Encoding the states so outputs come straight from state-register bits, or registering the outputs, gives glitch-free outputs.

Check your understanding

What characterizes a Mealy state machine?

  1. AOutputs depend only on the state and do not change until the next clock
  2. BOutputs depend on both current state and inputs, so input changes appear at the output within the same cycle
  3. CIt is combinational logic with no state
Show answer and explanation

Answer: B. Outputs depend on both current state and inputs, so input changes appear at the output within the same cycle

In a Mealy machine the output logic looks at inputs as well as the current state, so outputs change with inputs without waiting for a clock, reacting one cycle sooner. It may also need fewer states. But a combinational path runs from inputs to outputs, so input glitches can appear at outputs and timing paths get longer. Outputs are sometimes re-registered through flip-flops.

Which type of sequential circuit (state machine) has outputs determined only by the current state?

  1. AMealy machine
  2. BMoore machine
  3. CHarvard machine
Show answer and explanation

Answer: B. Moore machine

In a Moore machine, outputs depend only on the current state; in a Mealy machine, they depend on both state and inputs. Moore outputs change only after a clock edge and input changes or glitches do not pass straight to them, so they are stable and predictable, but they respond a clock later and often need more states. Mealy machines need fewer states and react immediately, but input changes pass directly to the outputs. Real designs mix both styles.

What is the basic structure of a state machine written in an HDL?

  1. AOnly memory to remember the state, with no logic
  2. BOnly output logic, with no memory of state
  3. CA register holding the current state, combinational logic choosing the next state, and combinational logic producing outputs
Show answer and explanation

Answer: C. A register holding the current state, combinational logic choosing the next state, and combinational logic producing outputs

A state machine keeps the current state in a flip-flop register, determines the next state from the current state and inputs with combinational logic, and updates the state at the clock edge. Outputs are produced from the current state (and inputs) by combinational logic. Many circuits that follow a procedure, such as protocol controllers, vending machines and traffic lights, are written as state machines.

  1. What is a characteristic of one-hot encoding for state machine states?
  2. For a state machine with three states, how many flip-flops are needed to store the state (binary encoding / one-hot encoding)?
  3. Which correctly describes a sequential circuit?

Practice HDL & Verification questions

Key terms explained

Mealy machine
A state machine whose outputs depend on both the current state and the inputs. Input changes reach outputs within the same cycle, but so can input glitches. A Moore machine's outputs depend only on state.
Sequential circuit
A logic circuit that stores state in flip-flops and the like, so its output depends on both inputs and past state. Examples include counters and registers.
Combinational circuit
A logic circuit whose output depends only on its current inputs. Examples include adders, multiplexers and decoders.
Flip-flop
The basic element of sequential circuits that stores one bit. A D flip-flop captures its input at a clock edge.
Glitch
An unwanted momentary pulse on an output, caused for example by differing delays along signal paths. In combinational logic it is also called a hazard; in DACs it appears when the code changes.
One-hot encoding
State encoding that assigns one flip-flop per state with exactly one set at a time. Logic tends to be simple and fast, and it is common on FPGAs.
Combinational loop
A structure in which combinational output feeds back to its own input without a flip-flop. It can oscillate or fail to settle and defeats timing analysis, so it is avoided.
Unintended latch
A latch created by synthesis when a description intended as combinational logic fails to assign an output under some condition, so the value must be held.

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