HDL & Verification

Intending combinational logic, someone writes the code above. What does logic synthesis produce?

always @(*) begin
    if (en)
        y = d;
end
  1. ACombinational logic where y automatically becomes 0 when en is 0
  2. BA clocked D flip-flop
  3. CBecause y must hold its value when en is 0, an unintended latch is created
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Answer: C. Because y must hold its value when en is 0, an unintended latch is created

When en is 0 nothing is assigned to y, so y must remember its previous value. Combinational logic has no memory, so synthesis creates a latch to hold it. Latches complicate timing analysis and can malfunction from glitches, so unintended ones are avoided. Assigning a value in every case, for example "else y = 0;", yields combinational logic.

  • A. Nothing assigns 0, so it does not become 0.
  • B. No clock is used, so it is not a flip-flop.
  • C. Correct. The missing else is the cause.
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More HDL & Verification questions

  1. Why does the code above create a latch, and what is the fix?
  2. Which coding style is commonly used to prevent unintended latches in combinational always blocks?
  3. Which Verilog construct is ignored by logic synthesis and does not become hardware (a simulation-only construct)?
  4. When the code above, which counts the 1s in 8-bit d, is synthesized, what kind of circuit results?
  5. What type of reset does the code above have, and how does it behave?