HDL & Verification

What is the difference between wire and reg in Verilog?

  1. AA reg always becomes a flip-flop and a wire always becomes combinational logic
  2. Bwire represents connections driven by assign statements and the like; reg is a signal assigned inside always blocks, but a reg does not necessarily become a flip-flop
  3. Cwire holds numbers and reg holds characters
Show answer and explanation

Answer: B. wire represents connections driven by assign statements and the like; reg is a signal assigned inside always blocks, but a reg does not necessarily become a flip-flop

In Verilog, signals driven by assign statements or module outputs are declared wire, and signals assigned inside always blocks are declared reg. reg looks like short for register, but assigned inside always @(*) it becomes combinational logic, not a flip-flop. Whether a flip-flop results depends on whether the value is updated on a clock edge. SystemVerilog allows both to be written as logic.

  • A. Despite the name, a reg can become combinational logic.
  • B. Correct. A reg in always @(*) becomes combinational logic.
  • C. Neither is a character type.
Practice this topic Back to topic

More HDL & Verification questions

  1. What circuit does the Verilog assign statement above represent?
  2. What circuit does logic synthesis create from the Verilog above?
  3. How does Verilog's nonblocking assignment (<=) behave?
  4. In the code above, a = 0 and b = 1 just before a rising clock edge. What are a and b after the edge?
  5. Intending a two-stage shift register, someone wrote the code above with blocking assignments (=). What goes wrong?