Advanced packaging (3D and chiplets)

In 3D NAND, which is a correct advantage of making the memory cell array and peripheral circuits on separate wafers and bonding them together?

  1. AThe manufacturing process always takes just one step
  2. BMemory cells become unnecessary
  3. CEach can be made with a process suited to it, and chip area can be reduced
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Answer: C. Each can be made with a process suited to it, and chip area can be reduced

Making the memory cell array and peripheral (CMOS) circuits on separate wafers with optimal processes and bonding them together puts the peripheral circuits under the memory cells, reducing chip area. Another advantage is that the peripheral circuits are not affected by the cell array's high-temperature steps.

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More Advanced packaging (3D and chiplets) questions

  1. What is the material called that is placed between a chip and a heat spreader to fill microscopic gaps and improve heat transfer?
  2. What is the data transfer capacity that can be secured per unit length of chip edge called, emphasized as a performance metric for chiplet interconnects?
  3. Which correctly describes the difference between 2.5D and 3D packaging?
  4. In HBM, what is the typical number of DRAM dies stacked in one stack?
  5. What is the concept called that integrates chips made with different manufacturing processes and materials into one package?