Advanced packaging (3D and chiplets)

Which is a challenge of moving to chiplets?

  1. AThe area and power of interface circuits connecting chips, and the effort of assembly and testing, increase
  2. BChip yield always falls
  3. CChips from different processes cannot be combined
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Answer: A. The area and power of interface circuits connecting chips, and the effort of assembly and testing, increase

With chiplets, connections that on-chip wiring handled in a monolithic design must pass through die-to-die interface circuits (PHYs), adding area, power and latency. Advanced packaging assembly, screening of good dies and post-stacking tests are also required. Adoption is therefore advancing in large chips where the benefits outweigh these costs.

  • A. Correct. The burden of interfaces and assembly increases.
  • B. Splitting into smaller chips actually tends to raise yield.
  • C. Being able to combine chips from different processes is one of the advantages.
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More Advanced packaging (3D and chiplets) questions

  1. What is the main aim of products that stack a cache SRAM chip on top of a processor chip with hybrid bonding?
  2. Which method is used to make silicon interposers larger than the maximum area a lithography tool can expose at once (about 26 mm × 33 mm)?
  3. Which correctly explains how copper electrodes are joined to each other in copper-dielectric hybrid bonding?
  4. In classifying TSVs by when they are formed, which approach makes TSVs after forming transistors but before forming the multilayer interconnect?
  5. Which pair of typical pitches (terminal spacing) for chip-to-chip connections is most appropriate?