Silicon Interposer vs Organic Interposer vs Silicon Bridge: Wiring Density, Size and Cost
In 2.5D packaging, several chips such as a processor and HBM stacks sit side by side and are connected by wiring much finer than a package substrate can offer. There are three main ways to provide that connection. A silicon interposer is a slab of silicon with fine wiring made by the wafer interconnect process, placed under all the chips. An organic interposer is built from redistribution layers (RDL) of polymer dielectric and copper wiring. A silicon bridge is a small piece of silicon with fine wiring embedded only under the areas where chips meet. The silicon interposer wins on wiring density, while the organic interposer and silicon bridge win on size and cost. The choice depends on how many connections are needed and how large the package is.
| Aspect | Silicon interposer | Organic (RDL) interposer | Silicon bridge |
|---|---|---|---|
| How it is made | Multilayer fine wiring (copper damascene, as in chip interconnects) and TSVs are built on a silicon wafer | Polymer dielectric layers (such as polyimide) and plated copper wiring are stacked layer by layer on a carrier | A small piece of silicon with fine wiring is embedded in the package substrate or in redistribution layers |
| Where silicon is placed | One large slab under all the chips | No silicon; redistribution layers sit under all the chips | Only under the adjacent edges of neighboring chips; other connections go through ordinary substrate wiring |
| Typical line width/spacing | Finest, typically around 1 µm or below | Coarser than silicon, typically around 2 µm, with fewer layers | As fine as a silicon interposer in the bridge area |
| Size limits | Going beyond one exposure field (about 26 mm × 33 mm) requires stitching exposures together, and cost rises with size | Easier to make large than a silicon interposer | Bridges themselves are small, so placing several of them makes packages larger than one exposure field easier |
| Need for TSVs | Required, to connect the chips on top through the interposer to the package substrate | Not needed; vias in the redistribution layers make vertical connections | In most substrate-embedded designs the bridge itself needs no TSVs; power and many signals connect directly to the substrate outside the bridge |
| Cost | High, needing a large silicon area and TSV processing | Easier to keep below a silicon interposer | Easier to keep below a silicon interposer because the silicon area is small, though embedding and alignment steps are added |
| Thermal expansion and warpage | Silicon expands much less with heat than organic substrates, and the resulting stress and warpage become harder to manage as size grows | Thermal expansion is close to the package substrate, which helps reduce stress at the joints, but warpage and dimensional change of the polymer layers must be controlled | Most of the package is organic substrate, so overall warpage is close to an ordinary substrate; local stress around the bridge and height control of fine and coarse bumps are challenges |
| Electrical characteristics | Wires are fine and short; fine wires have high resistance, so they are not suited to long runs | Thicker wires are easier, so resistance is lower, but wiring density is lower | Dense wiring covers only the short span between chip edges; power can be fed directly from the substrate without passing through the bridge |
| Typical uses | Connections that need very many wires, such as a processor with several HBM stacks | Chiplet connections where wiring demands are less severe or a large area is needed | Chiplet and HBM connections in large packages that need dense wiring only between chip edges |
Figures are typical orders of magnitude and vary by process generation and product.