Beyond Scaling: Where Semiconductor Technology Goes Next

Why scaling became hard

Moore's law, proposed in 1965, is the observation that the number of transistors on a chip doubles roughly every two years. For a long time, smaller transistors also allowed lower supply voltages through Dennard scaling, so chips got faster without raising power per unit area.

From around the mid-2000s, threshold and supply voltages became hard to lower further and leakage grew, so Dennard scaling broke down. Several walls remain today:

• Weaker gate control: as channels get shorter, current leaks even when the gate turns the transistor off (short-channel effects).
• Slower wires: thinner wires have higher resistance, increasing RC delay and power loss. Interconnect increasingly limits performance more than the transistors do.
• Lithography and manufacturing cost: printing finer patterns needs expensive tools such as EUV lithography and more process steps, so cost per transistor falls more slowly.
• Heat: packing more transistors into a small area makes heat harder to remove.

Note that node names such as "3 nm" or "2 nm" no longer describe a specific physical dimension like gate length; they are labels that distinguish generations.

The industry is therefore pushing in several directions at once: changing the transistor's shape, rerouting power wiring, stacking chips, using light instead of electrical signals, adopting materials other than silicon, and rethinking how memory and computation relate. The sections below take each in turn.

1. New transistor shapes: from FinFET to GAA and CFET

In a planar transistor, the gate touches only the top of the channel. The FinFET stands the channel up as a fin and wraps the gate around three sides for better control. GAA (gate-all-around) transistors go further, stacking thin channel ribbons (nanosheets) and surrounding them on all four sides. The industry has been moving to GAA at the 3 nm to 2 nm class nodes.

A candidate beyond that is the CFET (complementary FET), which stacks the nMOS and pMOS transistors vertically. It could build the same circuit in a smaller area and is under active development.

Backside power delivery, which moves the power wiring to the back of the wafer, is also entering production. It reduces congestion in the front-side wiring and cuts voltage drop. These technologies are developed with DTCO, which optimizes design and process together.

• Advanced transistors (FinFET and GAA) Try 10 questions

Compare: Planar MOSFET vs FinFET / FinFET vs GAA

High-k / metal gate Strained silicon FinFET GAA Nanosheet CFET Backside power delivery DTCO

2. Printing finer patterns: EUV and High-NA EUV

Lithography has driven scaling. EUV lithography, at a wavelength of 13.5 nm, prints in fewer steps patterns that needed repeated exposures with 193 nm ArF immersion lithography. High-NA EUV, which raises the optics' numerical aperture (NA) from 0.33 to 0.55, is now being introduced. It brings new challenges, including tool cost and an exposure field half the usual size. Directed self-assembly (DSA), which uses the regular patterns that polymers form on their own, is being studied in combination with EUV to reduce variation.

• Lithography Try 10 questions

Compare: EUV vs DUV lithography

3. Stacking and connecting: advanced packaging, 3D and chiplets

Instead of making one die bigger and finer, the industry increasingly connects several dies tightly inside one package. Splitting a design into smaller dies by function (chiplets) improves yield compared with one large die and lets each part use the most suitable process node.

Placing dies side by side on a silicon interposer is 2.5D packaging; stacking them vertically and connecting them with TSVs (through-silicon vias) and similar links is 3D packaging. AI GPUs use packaging such as CoWoS to place HBM (stacked DRAM dies) right beside the processor. Hybrid bonding joins dies directly through copper pads, giving far more connections at a finer pitch than solder bumps. UCIe was created as a standard die-to-die interface for chiplets.

Glass core substrates and panel-level packaging (PLP), which processes packages on large rectangular panels instead of round wafers, are drawing attention as next steps. Monolithic 3D integration, which builds transistor layers one after another on a single wafer instead of bonding dies, is also being researched.

• Advanced packaging (3D and chiplets) Try 10 questions

Compare: 2.5D vs 3D packaging / DDR vs LPDDR vs GDDR vs HBM

Chiplet 2.5D packaging 3D packaging TSV Hybrid bonding Silicon interposer Redistribution layer (RDL) CoWoS HBM UCIe

4. Connecting with light: silicon photonics

Electrical links that carry data off the chip lose more signal and burn more power as speeds rise. Silicon photonics, which builds optical circuits with silicon manufacturing techniques, lets signals travel as light instead. It is used in data-center optical transceivers, and CPO (co-packaged optics), which places the optical components in the same package as a processor or switch, is moving toward deployment. In Japan, efforts to bring optical and electronic circuits together and replace electrical wiring with light are often called photonics-electronics convergence. Because electrical losses grow with wire length, converting to light closer to the chip pays off.

• Silicon photonics Try 10 questions

5. Materials beyond silicon

Silicon is not the best choice for every job. In power conversion, wide-bandgap SiC (silicon carbide) and GaN (gallium nitride) are used in electric vehicles and fast chargers. Materials with even wider bandgaps, such as Ga2O3 (gallium oxide) and diamond, are being researched.

For logic transistors, researchers are studying two-dimensional materials only a few atomic layers thick as future channel materials. For interconnect, metals that could replace copper, whose resistance rises sharply in very narrow lines, are also being evaluated.

• Power semiconductors Try 10 questions
• Compound semiconductors Try 10 questions
• Interconnect processes Try 10 questions

Compare: Si vs SiC power semiconductors / SiC vs GaN

6. Rethinking memory and computation

In AI workloads, moving data between memory and the processor often costs more time and energy than the arithmetic itself. Besides placing memory closer, as HBM does, researchers are exploring in-memory computing, which computes inside or next to the memory. Neuromorphic computing, which mimics the brain's neural circuits and computes with spikes, is another attempt to cut data movement and power.

Memory itself is changing too. 3D NAND has grown capacity by stacking cells vertically, and research is under way to stack DRAM in a similar way (3D DRAM). Non-volatile memories such as MRAM, ReRAM and FeFET are starting to be used where they suit the application.

• Emerging memories Try 10 questions

Compare: MRAM vs ReRAM vs PCM vs FeRAM

7. Changing the principle of computing: quantum computers

Quite apart from shrinking transistors, researchers are building qubits, which compute using quantum superposition and entanglement. Qubits are fragile against decoherence, the loss of their quantum state through interaction with the environment, so superconducting transmons are cooled close to absolute zero in a dilution refrigerator. Silicon spin qubits attract attention because they can reuse semiconductor-fab manufacturing. Useful computation needs quantum error correction, in which many physical qubits protect one logical qubit, and semiconductor technology such as cryogenic CMOS control electronics plays a large part. Meanwhile, concern that future quantum computers could break today's public-key cryptography has started the move to post-quantum cryptography.

• Quantum Computing Hardware Try 10 questions

How to study these topics

New technologies are easier to understand once you know where today's technology hits its limits. Start by checking the basics in MOSFET and Lithography, then move on to the categories above. To cover the fabrication flow end to end, try the course "The fabrication process".